STABLE: Combining Satisfiability Solving, Boolean Reasoning and Computer Algebra for System-on-Chip Verification

This paper presents a new satisfiability (SAT) modulo Theory (SMT) solver, STABLE, for formulas of the quantifierfree logic over fixed-sized bit vectors (QF-BV). As the primary application domain for STABLE we target an SMT-based property checking flow for System-on-Chip (SoC) designs. STABLE integrates a computer-algebra-based engine which provides algorithms for proving arithmetic problem parts with a standard SAT approach, where an SMT instance is transformed into an equisatisfiable SAT-instance. To extend the scope of the computer-algebra engine we also include an extraction technique that derives required arithmetic information from gate-level parts of an instance. This is crucial when verifying industrial high performance data-paths where critical components have been optimized at the gate-level. STABLE was successfully evaluated in comparison with other state-of-the-art SMT solvers on a large collection of SMT formulas describing verification problems of industrial data path designs that include multiplication. In contrast to the other solvers STABLE was able to solve instances with bit-widths of up to 64 bits.